Rohankumar Patil is the FPGA Design and Verification Engineer at Scalable Systems Research Labs Inc based in Santa Clara, California, United States.
Rohankumar Patil
FPGA Design and Verification Engineer at Scalable Systems Research Labs Inc in Santa Clara, California, United States
Verified profile
r***@ssrlabs.com
Job Title
FPGA Design and Verification Engineer
Company
Scalable Systems Research Labs Inc
Location
Santa Clara, California, United States
Seniority
Entry
Work Email
r***@ssrlabs.com
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Colleagues at Scalable Systems Research Labs Inc
Other verified contacts at Scalable Systems Research Labs Inc.
Siddharth VenkataASIC Design Engineering Intern at Scalable Systems Research Labs IncChintan ParekhASIC Design & Verification Trainee at Scalable Systems Research Labs IncChandana BachhuASIC Design Engineer Intern at Scalable Systems Research Labs IncKiratey PatilJunior ASIC Design Engineer at Scalable Systems Research Labs IncSuchindran RaviDesign Engineer at Scalable Systems Research Labs IncLavanya DeshmukhProject Management Intern at Scalable Systems Research Labs IncArun DevendranJr ASIC Verification Engineer at Scalable Systems Research Labs IncDeepak PepallaJunior ASIC Design Engineer at Scalable Systems Research Labs Inc
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Rohankumar Patil is the FPGA Design and Verification Engineer at Scalable Systems Research Labs Inc.
Where is Rohankumar Patil based?
Santa Clara, California, United States.
Who is the FPGA Design and Verification Engineer at Scalable Systems Research Labs Inc?
Rohankumar Patil.
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