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Scalable Systems Research Labs Inc
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People at Scalable Systems Research Labs Inc
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Siddharth VenkataASIC Design Engineering InternChintan ParekhASIC Design & Verification TraineeRohankumar PatilFPGA Design and Verification EngineerChandana BachhuASIC Design Engineer InternKiratey PatilJunior ASIC Design EngineerSuchindran RaviDesign EngineerLavanya DeshmukhProject Management InternArun DevendranJr ASIC Verification EngineerDeepak PepallaJunior ASIC Design EngineerHarita BallaASIC EngineerHaoche LiuStrategic AdvisorAbhilash GandlaASIC Design Engineer InternAsif NFirmware Team LeaderVibha NarasimhaBusiness Intelligence AnalystAkash SharmaASIC Design EngineerJohny RosaryASIC Design Engineer InternVikram KDesign EngineerKV RenganathanDesign Verification EngineerRahul GalaASIC EngineerDhruv SaxenaASIC Design EngineerAxel KlothPresident & CEORishul NaikASIC Design EngineerVikram MohiteJr. Verification EngineerDhaivat MasterFirmware Design EngineerSukruth KrishnamurthyASIC Design EngineerRamnath GopikrishnanJunior ASIC Design InternAditya TripathiIndependent Contractor - Analog Design InternSassoun GostantianASIC Design EngineerKartik KanduriASIC Engineer