Kiratey Patil is the Junior ASIC Design Engineer at Scalable Systems Research Labs Inc based in San Jose, California, United States.
Kiratey Patil
Junior ASIC Design Engineer at Scalable Systems Research Labs Inc in San Jose, California, United States
Verified profile
k***@ssrlabs.com
Job Title
Junior ASIC Design Engineer
Company
Scalable Systems Research Labs Inc
Location
San Jose, California, United States
Seniority
Entry
Work Email
k***@ssrlabs.com
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Siddharth VenkataASIC Design Engineering Intern at Scalable Systems Research Labs IncChintan ParekhASIC Design & Verification Trainee at Scalable Systems Research Labs IncRohankumar PatilFPGA Design and Verification Engineer at Scalable Systems Research Labs IncChandana BachhuASIC Design Engineer Intern at Scalable Systems Research Labs IncSuchindran RaviDesign Engineer at Scalable Systems Research Labs IncLavanya DeshmukhProject Management Intern at Scalable Systems Research Labs IncArun DevendranJr ASIC Verification Engineer at Scalable Systems Research Labs IncDeepak PepallaJunior ASIC Design Engineer at Scalable Systems Research Labs Inc
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Kiratey Patil is the Junior ASIC Design Engineer at Scalable Systems Research Labs Inc.
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San Jose, California, United States.
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Kiratey Patil.
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