Chintan Parekh is the ASIC Design & Verification Trainee at Scalable Systems Research Labs Inc based in Mumbai, Maharashtra, India.
Chintan Parekh
ASIC Design & Verification Trainee at Scalable Systems Research Labs Inc in Mumbai, Maharashtra, India
Verified profile
c***@ssrlabs.com
Job Title
ASIC Design & Verification Trainee
Company
Scalable Systems Research Labs Inc
Location
Mumbai, Maharashtra, India
Seniority
Entry
Work Email
c***@ssrlabs.com
Chintan's full work email still locked
Free account. Verified against live company records.
You'll unlock:
- Chintan's full verified work email
- LinkedIn and full company profile
Colleagues at Scalable Systems Research Labs Inc
Other verified contacts at Scalable Systems Research Labs Inc.
Siddharth VenkataASIC Design Engineering Intern at Scalable Systems Research Labs IncRohankumar PatilFPGA Design and Verification Engineer at Scalable Systems Research Labs IncChandana BachhuASIC Design Engineer Intern at Scalable Systems Research Labs IncKiratey PatilJunior ASIC Design Engineer at Scalable Systems Research Labs IncSuchindran RaviDesign Engineer at Scalable Systems Research Labs IncLavanya DeshmukhProject Management Intern at Scalable Systems Research Labs IncArun DevendranJr ASIC Verification Engineer at Scalable Systems Research Labs IncDeepak PepallaJunior ASIC Design Engineer at Scalable Systems Research Labs Inc
Other people named Chintan Parekh
Different professionals who share this name.
Frequently asked
What is Chintan Parekh's email address?
Chintan Parekh's work email follows the pattern c***@ssrlabs.com. Reveal it free.
What does Chintan Parekh do?
Chintan Parekh is the ASIC Design & Verification Trainee at Scalable Systems Research Labs Inc.
Where is Chintan Parekh based?
Mumbai, Maharashtra, India.
Who is the ASIC Design & Verification Trainee at Scalable Systems Research Labs Inc?
Chintan Parekh.
Get Chintan Parekh's verified contact details
Reveal the full work email and more. Free to start.
Try ScraperCity Free →