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Jacob Levin

Verfication & FPGA RTL Design at Verisense in Israel

Verified profile j***@verisense.com
Job Title
Verfication & FPGA RTL Design
Company
Verisense
Location
Israel
Seniority
Entry
Work Email
j***@verisense.com
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Jacob Levin is the Verfication & FPGA RTL Design at Verisense based in Israel.

Colleagues at Verisense

Other verified contacts at Verisense.
Timur AskerovDesign & Verification Engineer at VerisenseGuy AbramovichSenior VLSI Engineer at VerisenseGoldy LeviVerification Engineer at VerisenseOfir HillelFPGA Design Engineer at VerisenseYehuda ShaikCEO at VerisenseHagai NavehVerification Engineer at VerisenseAvishay Tvila- at VerisenseBenhur PenkarTechnical Team Leader & Senior FPGA Designer at Verisense

Other people named Jacob Levin

Different professionals who share this name.
Jacob LevinMarketing Director at GopuffJacob LevinBusiness Analyst at Quicken LoansJacob LevinForeign Service Officer at Us Department of StateJacob LevinFounder & Coo at SparkPlugJacob LevinProject Engineer 2 at JE Dunn Construction

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Jacob Levin is the Verfication & FPGA RTL Design at Verisense.

Who is the Verfication & FPGA RTL Design at Verisense?

Jacob Levin.

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