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Verisense
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People at Verisense
24 on file. Each links to their full profile, colleagues, and similar roles.
Timur AskerovDesign & Verification EngineerGuy AbramovichSenior VLSI EngineerGoldy LeviVerification EngineerOfir HillelFPGA Design EngineerYehuda ShaikCEOHagai NavehVerification EngineerAvishay Tvila-Benhur PenkarTechnical Team Leader & Senior FPGA DesignerUdi BarelVP EngineeringEitan MansharofSenior Design EngineerMeir MaromVerification EngineerBarak BaronVerification EngineerDavid MoscovitzFPGA & Board Design EngineerDan BouhnikCoordinatorAharon MalachiverificationLior HalabiVerification EngineerMoti GabbayLogic Design EngineerMichal PeregHardware EngineerChagay SaboVerification EngineerIshay HazanVLSI Senior Verification EngineerAri BenporatJunior Verification EngineerJacob LevinVerfication & FPGA RTL DesignMoria ShrikiLogic Design EngineerJonathan LubatVerification Engineer