Josko Rokov is the FPGA design engineer at Intesis based in Croatia.
Josko Rokov
FPGA design engineer at Intesis in Croatia
Verified profile
j***@intesis.cl
Job Title
FPGA design engineer
Company
Intesis
Location
Croatia
Seniority
Entry
Work Email
j***@intesis.cl
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Colleagues at Intesis
Other verified contacts at Intesis.
Guillermo QuevedoAdministrador de Bases de Datos Senior at IntesisPablo LeibleGerente de Negocio Industria Financiera at IntesisJaqueline KriegerIngeniero de Software at IntesisCesar CabreraGerente de cuentas Salud Publica at IntesisVictor IbarraCoordinador de Microinformatica at IntesisYesid Leonmantenimiento at IntesisMarcela QuirogaIT Solution Architect at IntesisPaola LupanoConsultor Metodológico, PMO at Intesis
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Josko Rokov is the FPGA design engineer at Intesis.
Who is the FPGA design engineer at Intesis?
Josko Rokov.
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