Jorge Pagulayan is the IC Layout Engineer (Staff), Project Leader, Technical Manager, Trainer at Lattice Semiconductor based in Metro Manila, Philippines.
Jorge Pagulayan
IC Layout Engineer (Staff), Project Leader, Technical Manager, Trainer at Lattice Semiconductor in Metro Manila, Philippines
Verified profile
j***@latticesemi.com
Job Title
IC Layout Engineer (Staff), Project Leader, Technical Manager, Trainer
Company
Lattice Semiconductor
Location
Metro Manila, Philippines
Seniority
Manager
Work Email
j***@latticesemi.com
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Colleagues at Lattice Semiconductor
Other verified contacts at Lattice Semiconductor.
Lintao WuIP development engineer at Lattice SemiconductorDaryl MotodaBusiness Process, Senior Director at Lattice SemiconductorYoungtag WooSr Device Engineer at Lattice SemiconductorYoshita YerramilliDesign Engineer at Lattice SemiconductorQinglin YunSystem Validation Engineer at Lattice SemiconductorKathy HowePayroll Admin at Lattice SemiconductorBurdette RobbRealibility / Enviromental Lab Manager at Lattice SemiconductorHelmut DemelStaff Field Application Engineer at Lattice Semiconductor
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Jorge Pagulayan is the IC Layout Engineer (Staff), Project Leader, Technical Manager, Trainer at Lattice Semiconductor.
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Metro Manila, Philippines.
Who is the IC Layout Engineer (Staff), Project Leader, Technical Manager, Trainer at Lattice Semiconductor?
Jorge Pagulayan.
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