Jet Wu is the Senior Analog Circuit Design Engineer at Verisilicon Holdings Co Ltd based in China.
Jet Wu
Senior Analog Circuit Design Engineer at Verisilicon Holdings Co Ltd in China
Verified profile
j***@verisilicon.com
Job Title
Senior Analog Circuit Design Engineer
Company
Verisilicon Holdings Co Ltd
Location
China
Seniority
Senior
Work Email
j***@verisilicon.com
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Other verified contacts at Verisilicon Holdings Co Ltd.
Sam Chaisystem director at Verisilicon Holdings Co LtdYongjun Chenprinciple engineer, gpu/vision ip design/ASIC at Verisilicon Holdings Co LtdSean ZouIT & CAD at Verisilicon Holdings Co LtdYabo WangPurchasing Director at Verisilicon Holdings Co LtdWei GaoSenior Engineer of SOC verification at Verisilicon Holdings Co LtdJanet ZhaoFinance Manager at Verisilicon Holdings Co LtdHuiming ZhangDirector of Hardware Development at Verisilicon Holdings Co LtdMankit LoSenior Director of Vision Image Development at Verisilicon Holdings Co Ltd
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Jet Wu is the Senior Analog Circuit Design Engineer at Verisilicon Holdings Co Ltd.
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Jet Wu.
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