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Hdl Design House
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People at Hdl Design House
84 on file (showing 60). Each links to their full profile, colleagues, and similar roles.
Nikos GeorgoulopoulosASIC Verification EngineerBogdan BizicManaging DirectorMilica BjelanovicVerification EngineerJelena DimovJunior Analog EngineerJovana TrivicIT engineerBozidar NikolicDigital Design EngineerDusan MaticVerification EngineerDusan StanisicVerification EngineerDragan MarkovicQuality ManagerChristoforos GliasASIC Verification EngineerMladen CicmilAnalog Design EngineerDimitrios KampasVerification EngineerSrdan SelimovskiJunior Verification EngineerMilos VujanovicJunior IT EngineerIvan RisticASIC Verification EngineerVladimir KosjerJunior Design and Verification EngineerMarija ObradovicJunior Verification EngineerZarko AcimovicVerification EngineerPetros Mytis-GkomethDesign Verification EngineerSafiye CevikMuhasebeBranko BaracJunior Design EngineerHanafi Kamalla livresonDimitrije MarkovicHuman Resources ManagerJelena PopovicDesign Verification EngineerMarija MazibradaVerification EnginneerNikola GacicDesign Verification EngineerMilica KrunicJunior Verification EngineerJovana PavlovicVerification EngineerStela Araujoaux de produçãoPredrag MarkovicPresident/CEODimitrios SamarasAnalog Design EngineerOlja StrugarDesign Verification EngineerMarija UgarakPrincipal Verification EngineerKaterina KefalaVerification EngineerStefanija DacicVerification EngineerAna GajicDesign Verification EngineerMilomir MatijevicVerification EngineerZoran StankovicSenior Verification EngineerSvetozar MojsinCFOBogdan MitrovicDigital Design and Verification EngineerNikola EskicJunior Design EngineerDimosthenis TastzoglouVerification EngineerZora MihaljcicVerification EngineerMarelas GeorgeJunior ASIC Verification EngineerAnke VerduinCreative DirectorChristos VakerlisVerification EngineerObrad MilicevicVerification EngineerJelena KovacevicVerification EngineerIoannis GiannouASIC/FPGA SoC Verification Engineer at HDL Design HouseMilica RadicVerification EngineerRich KellaherSales ManagerStevan StevanovicDigital Design EngineerNikos GavriilidisVerification EngineerMarko DutinaVerification EngineerMilos CapinJunior analog engineerMiodrag PavlovicDesign Verification EngineerJelso ManuelDelivery DriverXanthos VlachosASIC/FPGA Digital Design EngineerEpistimi ProiskouJunior Analog Design EngineerRomaios-Christos KyriakosDesign Verification Engineer